1. Field of the Invention
The present invention relates generally to testing of integrated circuits (IC) and more particularly relates to generation of deterministic partially specified test vectors for built-in-self-test of ICs.
2. Background Information
An unprecedented proliferation of very large scale integrated (VLSI) circuits is accompanied by quickly increasing cost of their testing which in many areas became a major or even predominant component of the overall costs associated with manufacturing and shipping of integrated circuits. This is largely because contemporary test system technologies continue to follow traditional methodologies in which test vectors are applied and test responses are analyzed by means of an expensive external testing equipment. With rising off-chip frequencies and chip pad counts being highly unbalanced by increasing complexity of circuits, there is an indispensable need to use lower-priced test systems enhancing the traditional test methods in terms of reduced dependency on physical probes, at-speed test capabilities, increased test portability, and significantly reduced test costs.
In built-in self-test (BIST) approach, now an emerging means of testing and alternative for conventional techniques, on-chip hardware both generates test patterns and evaluates output data. Test patterns are typically generated by a test pattern generator, and output data evaluation usually consists of a test response compaction, in which multiple-input signature registers (MISRs) compact output sequences of a circuit under test (CUT) into a few-bit signature. The general state of the art in this well established area can be illustrated by, for example, V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A Tutorial on Built-In Self Test. Part 1: Principles", IEEE Design and Test of Computers, March 1993, pp. 73-82, and V. D. Agrawal, C. R. Kime, and K. K. Saluja, "A Tutorial on Built-In Self-Test. Part 2: Applications", IEEE Design and Test of Computers, June 1993, pp. 69-73.
An efficient test pattern generator which guarantees complete fault coverage while minimizing test application time, area overhead, and test data storage is essential for a successful BIST scheme. Many different generation schemes have been proposed to accomplish various tradeoffs between these parameters. The solutions range from pseudo-random techniques that do not use any storage but take a long application time and often do not detect some faults, to deterministic techniques that may require significant test data storage but achieve complete fault coverage in a relatively short time. Pseudo-random test patterns are typically generated using pseudo-random pattern generators (PRPG), such as Linear Feedback Shift Registers (LFSR) constituted with flip-flops and XOR gates. Again, the aforementioned literature items provide a good reference point to the state of the art in this area.
Mixed-mode test pattern generation is an attractive alternative to the above scenarios. It uses pseudo-random patterns to cover easy-to-test faults and, subsequently, deterministic patterns to target the remaining hard-to-test faults. As opposed to other approaches, such as test point insertion, mixed-mode techniques can reach complete fault coverage without imposing circuit modifications and causing performance degradation. Moreover, it is possible to obtain different trade-offs between test data storage and test application time by varying the relative number of deterministic and pseudo-random patterns. However, the overall efficiency of BIST scheme resting on mixed-mode generators strongly depends on the methods employed to reduce the amount of test data.
There are two main approaches to reduce the quantity of test data: (1) reduction of the number of deterministic patterns by using dynamic compaction algorithms that target several single faults with a single pattern; and (2) compression of deterministic test cubes by exploiting the fact that frequently they feature a large number of unspecified positions. One of the methods to compress test cubes is based on the reseeding of LFSR and has been originally proposed by B. Koeneinann in the paper entitled "LFSR-Coded Test Patterns for Scan Designs", in Proc. European Test Conf, Munich 1991, pp. 237-242. A comprehensive analysis of this scheme as well as a new reseeding scenario based on Multiple Polynomial Linear Feedback Shift Registers (MP-LFSRs) has been provided by S. Hellebrand, J. Rajski, S. Tamick, S. Venkataraman and B. Courtois in the paper entitled "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE Trans. on Computers, vol, C44, Feb. 1995, pp. 223-233. A similar technique has been also discussed by S. Hellebrand, B. Reeb, S. Tarnick, and H.-J. Wunderlich in the paper entitled "Pattern Generation for a Deterministic BIST Scheme", in Proc. ICCAD, November 1995, pp. 88-94. An MP-LFSR is a LFSR whose XOR gates are selectively controlled e.g. by AND gates, depending on the characteristic polynomial to be represented. Using this method, a concatenated group of test cubes with a total of s specified bits is encoded with approximately s bits specifying a seed and a polynomial identifier. The content of the MP-LFSR is loaded for each test group and has to be preserved during the decompression of each test cube within the group. Accordingly, the implementation of the decompressor may involve adding many extra flip-flops, even if flip-flops of the LFSR are used for the first k bits, in order to avoid overwriting the content of the MP-LFSR during the decompression of a group of test patterns,
An alternative to concatenation was proposed by N. Zacharia, J. Rajski, and J. Tyszer in the paper entitled "Decompression of Test Data using Variable-Length Seed LFSRs", Proc. VLSI Test Symposium, Princeton 1995, pp. 426-433. The underlying idea rests on the concept of variable-length seeds. Deterministic patterns are generated by an LFSR loaded with seeds whose lengths may be smaller than the size of the LFSR. Allowing such "shorter" seeds yields high encoding efficiency even for test cubes with varying number of specified positions. The decompression hardware is loaded for each test pattern. Hence, it is possible to implement the decompressor by using flip-flops of the scan chain, as the state of the decompressor can be overwritten between applications of test cubes. This is in contrast to the former technique which cannot share flip-flops with the scan chain, because the content of the MP-LFSR has to be preserved between decompressions of test cubes. As a result, the decompressor can be implemented without adding extra flip-flops, i.e. using the flip-flops of the LFSR and some of the flip-flops of the scan chain.
Since many ICs designed for testability include multiple scan chains, thus it is desirable to be able to extend the above described variable length reseeding technique to ICs designed to be tested with multiple scan chains.
Furthermore, one of the major advantages of BIST is its ability to operate at different levels of a circuit's architectural hierarchy. However, in order to invoke the BIST procedures and facilitate their correct execution at the board, module or system level, certain design rules must be applied. In 1990, a new testing standard was adopted by the Institute of Electrical and Electronics Engineers, Inc., and is now defined as tine IEEE Standard 1149.11 IEEE Standard Test Access Port and Boundary-Scan Architecture. Its overview can be found in The Test Access Port and Boundary-Scan Architecture by C. M. Maunder and R. E. Tulloss, IEEE Computer Society Press, 1990. The basic architecture of boundary-scan is incorporated at the integrated circuit level and essentially consists of a protocol by which various test functions can be carried out. In particular, the standard defines four (or optionally, five) new pins forming the Test Access Port (TAP): two of them (Test Clock TCK and Test Mode Select TMS) are used to control the protocol, while the remaining two pins (Test Data In TDI and Test Data Out TDO) are employed to serially shift data into and out of the circuit. The standard also specifies a simple finite state machine called the TAP controller which is driven by TCK and TMS.
Every chip designed according to the standard contains a boundary-scan Instruction Register and associated decode logic. It is used to set the mode of operation for selected data registers by means of boundary-scan instructions which always place data registers between TDI and TDO. Two registers must be always present; the Bypass Register and the Boundary Register. Several additional registers are allowed under the optional clause of the 1149.1, and they can be selected by sending the proper control sequences to the TAP controller.
Thus, it is further desirable if the variable reseeding technique can be extended to ICs designed to be tested with multiple scan chains in a manner that is compatible with the above described IEEE boundary scan architecture.